PREAMPLIFIER/A-D CONVERTER SYSTEM

We have built a preamplifier and A-D converter system as a single unit which is mounted right at the hermetic connector at the dewar wall [11]. In this manner the system is immune to electronic pickup noise that was formerly induced in the long coaxial cables that ran from the camera dewar to the electronics rack. The circuit is shown in Figure 4. The system uses a current sink for each array output that draws 500 $\mu$ A. The signal is amplified with a gain of 6 (or 18) and then processed by a Correlated Double Sampling (CDS) integrated circuit [12]. In fact, this is more conventionally a ``delta reset" circuit. The CDS circuit performs an analog subtraction between the full pixel level and the reset pixel level of the output waveform. The subtracted signal is then sampled by a 14 bit A-D converter. The digital data is buffered and transmitted serially over twisted pair to a receiver in the electronics rack. The data is then loaded into the coadder DSP to construct the image.

**Figure 4:** Schematic of the preamplifier/A-D circuit. The FPA output at the left is driven by a current sink, and amplified. The resulting signal is shown shown below the circuit, with a period of 2.4 $\mu$ sec/pix. Sample and Hold 1 is applied at the full pixel value, S/H 2 at the reset pixel value. The CDS circuit performs an analog subtraction which is shown with with the location of the A-D start pulse. The data is sent to the coadders on a twisted pair.
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**Figure 5:** Six histograms resulting from sampling waveforms with the preamplifier/A-D system. The amplitude of the waveform at the A-D is given on the graph. The FWHM of the distributions is less than 2 ADC units.
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Tests of the preamplifier system at a speed of 2.4 $\mu$ sec/pixel show that the system has an accuracy of better than 2 ADC units FWHM. Figure 5 shows histograms for 6 input waveform amplitudes: 0.167, 0.667, 1.5 V, with a gain of 6; and 0.056, 0.222, 0.5 V, with a gain of 18. Note that the maximum array output amplitude is 1.4 V. In the figure each voltage case has been shifted along the x axis so that they appear on the same graph. The system demonstrates better than 12 bit accuracy. It should be mentioned that the development of a test signal which is synchronized with the collection system and has an accuracy of better than 13 bits required care and attention in and of itself.