To ensure a good startup after a saddle bag power off and on, we should shutdown the processes on the crate that may error when electronis are powered down. The processes in question are the broadcast monitor and the dewar temperature servo. If these processes are running, it is difficult to bring up the crate.
Example crate output from the shutdown
When the CCD Controller electronics is initially powered, the only power supply that comes on initially is the +5-volt digital power. The analog supplies are not enabled onto the controller's backplane until a power-up selftest sequence completes. Similarly, no bias voltages or clocks are applied to the CCD mosaic until all such voltages have been checked. Thus, when the CCD controller is first turned on, the analog portions of the video processing circuitry will have no analog power and the CCD mosaic will have no power. If you attempt to read out an image with the controller in that state, you will get a totally flat image (i.e., all pixels having the same random value). If you have also power-cycled or rebooted the CCD VME crate prior to attempting to power-up the CCD controller, then see Restarting LRIS-R crate (below) , then return to this procedure.
If the LRIS-R CCD VME crate is power-cycled or rebooted, at present it will simply reload the VxWorks system but will not load the LRIS-R application code.
To load the VxWorks application and start the 4 basic LRIS tasks (cserv, responder, MLOG..., rccd) running:
-> shutdown Have entered shutdown routine Setting exit flags for monitor processes Waiting for monitor processes to shutdown Sending STP command to TIMING board Sending SBV command to TIMING board Sending LOR command to TIMING board Analog switches in dewar electronics commanded open Analog switches in dewar electronics indicate open Analog power has been commanded off Now switch off main power at controller value = 0 = 0x0
-> tdl 0,1 msg = 0X103 0X54444c 0Xffffff reply = 0X10002 0Xffffff reply = 0X10002 0Xffffff value = 0 = 0x0 -> tdl 0,2 msg = 0X203 0X54444c 0Xffffff reply = 0X20002 0Xffffff reply = 0X20002 0Xffffff value = 0 = 0x0 -> tdl 0,3 msg = 0X303 0X54444c 0Xffffff reply = 0X30002 0Xffffff reply = 0X30002 0Xffffff value = 0 = 0x0
restart
startup("/vx/lrisredm/dsp",0)
Sending STP command to TIMING board
Sending LOR command to TIMING board
UTB application 0 test location= 10
UTB digital output= f9d8
Analog switches in dewar electronics commanded open
Sending hardware reset to TIMING board
msg size = 2 words. reply size = 2 words
msg = 0X102 0X54544852
reply = 0X10002 0X444f4e
Sending STP command to TIMING board
Will verify vmeinf eprom against /vx/lrisredm/dsp/vmeinf/vme.s
VMEINF board verification status= 0, should be 0
Will verify timing eprom against /vx/lrisredm/dsp/timing/timing.s
TIMING board verification status= 0, should be 0
Will verify utility eprom against /vx/lrisredm/dsp/utility/util.s
Expecting 1 verification error: at 800081
verify error: at address 800081 expected: 000004 got: 052d79
EOF
UTILITY board verification status= 1, should be 1
EEPROMs verified correctly. Proceeding with power-up
msg size = 3 words. reply size = 2 words
msg = 0X303 0X4c4c4441 0X0
reply = 0X30002 0X444f4e
Application 0 loaded on utility board
CCD shutter commanded to the closed state
EEPROMs OK, so about to turn on analog power
PON command sent to the utility board
+5v readback raw ADC reading = 3427 volts= 5.042675 prior to enables
+15v readback raw ADC reading = 3516 voltage = 16.507736 prior to enable
-15v readback raw ADC reading = 592 voltage = -16.372795 prior to enable
+30v readback raw ADC reading = 3289 volts = 34.819450 prior to enable
UTB digital output= ff80
Analog switches in dewar electronics commanded open
Analog switches in dewar electronics indicate open
Bias and clock voltages have been set, but not yet sent to CCD
High voltage substrate has been set, but not yet sent to CCD
Getting raw ADC channel 0 of utility board for camera 0
Got raw analog data.
Send response to host.
Bias voltages for CCD 1
CCD 1 bias 0 ADC 2713 ( a99) MUX 0.971 Volts 27.900 HVS
CCD 1 bias 1 ADC 2048 ( 800) MUX -0.001 Volts -0.015 unused
CCD 1 bias 2 ADC 368 ( 170) MUX -2.458 Volts -24.723 VDD-L
CCD 1 bias 3 ADC 930 ( 3a2) MUX -1.636 Volts -16.523 RD-L
CCD 1 bias 4 ADC 376 ( 178) MUX -2.446 Volts -24.704 VDD-U
CCD 1 bias 5 ADC 2320 ( 910) MUX 0.396 Volts 0.796 OG-U
CCD 1 bias 6 ADC 2320 ( 910) MUX 0.396 Volts 0.788 OG-L
CCD 1 bias 7 ADC 2048 ( 800) MUX -0.001 Volts -0.001 unused
CCD 1 bias 8 ADC 3261 ( cbd) MUX 1.772 Volts 6.999 TG clock
CCD 1 bias 9 ADC 930 ( 3a2) MUX -1.636 Volts -16.523 RD-U
CCD 1 bias 10 ADC 2048 ( 800) MUX -0.001 Volts -0.003 unused
CCD 1 bias 11 ADC 1702 ( 6a6) MUX -0.507 Volts -2.004 clocks
CCD 1 bias 12 ADC 2048 ( 800) MUX -0.001 Volts 0.000 Ground
CCD 1 bias 13 ADC 2048 ( 800) MUX -0.001 Volts 0.000 Ground
CCD 1 bias 14 ADC 2048 ( 800) MUX -0.001 Volts 0.000 Ground
CCD 1 bias 15 ADC 2048 ( 800) MUX -0.001 Volts 0.000 Ground
Bias voltages for CCD 2
CCD 2 bias 0 ADC 2713 ( a99) MUX 0.971 Volts 27.900 HVS
CCD 2 bias 1 ADC 2048 ( 800) MUX -0.001 Volts -0.015 unused
CCD 2 bias 2 ADC 369 ( 171) MUX -2.456 Volts -24.709 VDD-L
CCD 2 bias 3 ADC 1038 ( 40e) MUX -1.478 Volts -14.929 RD-L
CCD 2 bias 4 ADC 377 ( 179) MUX -2.444 Volts -24.689 VDD-U
CCD 2 bias 5 ADC 2286 ( 8ee) MUX 0.346 Volts 0.696 OG-U
CCD 2 bias 6 ADC 2286 ( 8ee) MUX 0.346 Volts 0.690 OG-L
CCD 2 bias 7 ADC 2048 ( 800) MUX -0.001 Volts -0.001 unused
CCD 2 bias 8 ADC 2755 ( ac3) MUX 1.032 Volts 4.077 TG clock
CCD 2 bias 9 ADC 1038 ( 40e) MUX -1.478 Volts -14.929 RD-U
CCD 2 bias 10 ADC 2048 ( 800) MUX -0.001 Volts -0.003 unused
CCD 2 bias 11 ADC 1703 ( 6a7) MUX -0.506 Volts -1.998 clocks
CCD 2 bias 12 ADC 2048 ( 800) MUX -0.001 Volts 0.000 Ground
CCD 2 bias 13 ADC 2048 ( 800) MUX -0.001 Volts 0.000 Ground
CCD 2 bias 14 ADC 2048 ( 800) MUX -0.001 Volts 0.000 Ground
CCD 2 bias 15 ADC 2048 ( 800) MUX -0.001 Volts 0.000 Ground
Open bias voltages are all within tolerance
Bias and clock voltages restored following initial check.
Low-rail clock voltages for clock gen 1
CLKGEN 1 clock 0 ADC 1703 ( 6a7) MUX -0.505 Volts -1.995
CLKGEN 1 clock 1 ADC 1702 ( 6a6) MUX -0.507 Volts -2.001
CLKGEN 1 clock 2 ADC 1702 ( 6a6) MUX -0.507 Volts -2.001
CLKGEN 1 clock 3 ADC 1219 ( 4c3) MUX -1.214 Volts -4.794
CLKGEN 1 clock 4 ADC 1270 ( 4f6) MUX -1.139 Volts -4.499
CLKGEN 1 clock 5 ADC 1270 ( 4f6) MUX -1.139 Volts -4.499
CLKGEN 1 clock 6 ADC 1270 ( 4f6) MUX -1.139 Volts -4.499
CLKGEN 1 clock 7 ADC 1270 ( 4f6) MUX -1.139 Volts -4.499
CLKGEN 1 clock 8 ADC 1270 ( 4f6) MUX -1.139 Volts -4.499
CLKGEN 1 clock 9 ADC 1219 ( 4c3) MUX -1.214 Volts -4.794
CLKGEN 1 clock 10 ADC 890 ( 37a) MUX -1.695 Volts -6.697
CLKGEN 1 clock 11 ADC 752 ( 2f0) MUX -1.898 Volts -7.495
CLKGEN 1 clock 12 ADC 1702 ( 6a6) MUX -0.507 Volts -2.001
CLKGEN 1 clock 13 ADC 1702 ( 6a6) MUX -0.507 Volts -2.001
CLKGEN 1 clock 14 ADC 1702 ( 6a6) MUX -0.507 Volts -2.001
CLKGEN 1 clock 15 ADC 1184 ( 4a0) MUX -1.265 Volts -4.997
CLKGEN 1 clock 16 ADC 1269 ( 4f5) MUX -1.141 Volts -4.505
CLKGEN 1 clock 17 ADC 1270 ( 4f6) MUX -1.139 Volts -4.499
CLKGEN 1 clock 18 ADC 1270 ( 4f6) MUX -1.139 Volts -4.499
CLKGEN 1 clock 19 ADC 1270 ( 4f6) MUX -1.139 Volts -4.499
CLKGEN 1 clock 20 ADC 1270 ( 4f6) MUX -1.139 Volts -4.499
CLKGEN 1 clock 21 ADC 1184 ( 4a0) MUX -1.265 Volts -4.997
CLKGEN 1 clock 22 ADC 890 ( 37a) MUX -1.695 Volts -6.697
CLKGEN 1 clock 23 ADC 890 ( 37a) MUX -1.695 Volts -6.697
High-rail clock voltages for clock gen 1
CLKGEN 1 clock 0 ADC 2844 ( b1c) MUX 1.165 Volts 4.604
CLKGEN 1 clock 1 ADC 2844 ( b1c) MUX 1.165 Volts 4.604
CLKGEN 1 clock 2 ADC 2844 ( b1c) MUX 1.165 Volts 4.604
CLKGEN 1 clock 3 ADC 2913 ( b61) MUX 1.266 Volts 5.003
CLKGEN 1 clock 4 ADC 3085 ( c0d) MUX 1.518 Volts 5.997
CLKGEN 1 clock 5 ADC 3085 ( c0d) MUX 1.518 Volts 5.997
CLKGEN 1 clock 6 ADC 3085 ( c0d) MUX 1.518 Volts 5.997
CLKGEN 1 clock 7 ADC 3085 ( c0d) MUX 1.518 Volts 5.997
CLKGEN 1 clock 8 ADC 3224 ( c98) MUX 1.722 Volts 6.801
CLKGEN 1 clock 9 ADC 2913 ( b61) MUX 1.266 Volts 5.003
CLKGEN 1 clock 10 ADC 2221 ( 8ad) MUX 0.253 Volts 1.001
CLKGEN 1 clock 11 ADC 2221 ( 8ad) MUX 0.253 Volts 1.001
CLKGEN 1 clock 12 ADC 2844 ( b1c) MUX 1.165 Volts 4.604
CLKGEN 1 clock 13 ADC 2844 ( b1c) MUX 1.165 Volts 4.604
CLKGEN 1 clock 14 ADC 2844 ( b1c) MUX 1.165 Volts 4.604
CLKGEN 1 clock 15 ADC 2913 ( b61) MUX 1.266 Volts 5.003
CLKGEN 1 clock 16 ADC 3172 ( c64) MUX 1.646 Volts 6.500
CLKGEN 1 clock 17 ADC 3172 ( c64) MUX 1.646 Volts 6.500
CLKGEN 1 clock 18 ADC 3172 ( c64) MUX 1.646 Volts 6.500
CLKGEN 1 clock 19 ADC 3172 ( c64) MUX 1.646 Volts 6.500
CLKGEN 1 clock 20 ADC 3172 ( c64) MUX 1.646 Volts 6.500
CLKGEN 1 clock 21 ADC 2913 ( b61) MUX 1.266 Volts 5.003
CLKGEN 1 clock 22 ADC 2221 ( 8ad) MUX 0.253 Volts 1.001
CLKGEN 1 clock 23 ADC 2221 ( 8ad) MUX 0.253 Volts 1.001
Open clock voltages are all within tolerance
Switch states set to select clock low rails
UTB digital output= ffd8
Analog switches commanded closed.
Analog switches in dewar electronics indicate closed
+5v readback raw ADC reading = 3426 volts= 5.039018 after closure
+15v readback raw ADC reading = 3516 voltage = 16.507736 after closure
-15v readback raw ADC reading = 592 voltage = -16.372795 after closure
+30v readback raw ADC reading = 3283 volts = 34.651104 after closure
Readccd task is still alive
CCD is now powered up, except for HVS.
Bias voltages for CCD 1
CCD 1 bias 0 ADC 2048 ( 800) MUX -0.001 Volts -0.042 HVS
CCD 1 bias 1 ADC 2048 ( 800) MUX -0.001 Volts -0.015 unused
CCD 1 bias 2 ADC 377 ( 179) MUX -2.444 Volts -24.591 VDD-L
Invalid voltage -24.591 for VDD-L on CCD 1; should be -24.700
CCD 1 bias 3 ADC 931 ( 3a3) MUX -1.635 Volts -16.508 RD-L
CCD 1 bias 4 ADC 384 ( 180) MUX -2.434 Volts -24.586 VDD-U
Invalid voltage -24.586 for VDD-U on CCD 1; should be -24.700
CCD 1 bias 5 ADC 2320 ( 910) MUX 0.396 Volts 0.796 OG-U
CCD 1 bias 6 ADC 2320 ( 910) MUX 0.396 Volts 0.788 OG-L
CCD 1 bias 7 ADC 2048 ( 800) MUX -0.001 Volts -0.001 unused
CCD 1 bias 8 ADC 1076 ( 434) MUX -1.423 Volts -5.619 TG clock
CCD 1 bias 9 ADC 931 ( 3a3) MUX -1.635 Volts -16.508 RD-U
CCD 1 bias 10 ADC 2048 ( 800) MUX -0.001 Volts -0.003 unused
CCD 1 bias 11 ADC 1703 ( 6a7) MUX -0.506 Volts -1.998 clocks
CCD 1 bias 12 ADC 2048 ( 800) MUX -0.001 Volts 0.000 Ground
CCD 1 bias 13 ADC 2048 ( 800) MUX -0.001 Volts 0.000 Ground
CCD 1 bias 14 ADC 2048 ( 800) MUX -0.001 Volts 0.000 Ground
CCD 1 bias 15 ADC 2048 ( 800) MUX -0.001 Volts 0.000 Ground
Bias voltages for CCD 2
CCD 2 bias 0 ADC 2048 ( 800) MUX -0.001 Volts -0.042 HVS
CCD 2 bias 1 ADC 2048 ( 800) MUX -0.001 Volts -0.015 unused
CCD 2 bias 2 ADC 377 ( 179) MUX -2.444 Volts -24.591 VDD-L
CCD 2 bias 3 ADC 1039 ( 40f) MUX -1.477 Volts -14.914 RD-L
CCD 2 bias 4 ADC 385 ( 181) MUX -2.433 Volts -24.571 VDD-U
CCD 2 bias 5 ADC 2286 ( 8ee) MUX 0.346 Volts 0.696 OG-U
CCD 2 bias 6 ADC 2286 ( 8ee) MUX 0.346 Volts 0.690 OG-L
CCD 2 bias 7 ADC 2048 ( 800) MUX -0.001 Volts -0.001 unused
CCD 2 bias 8 ADC 1700 ( 6a4) MUX -0.510 Volts -2.015 TG clock
CCD 2 bias 9 ADC 1039 ( 40f) MUX -1.477 Volts -14.914 RD-U
CCD 2 bias 10 ADC 2048 ( 800) MUX -0.001 Volts -0.003 unused
CCD 2 bias 11 ADC 1703 ( 6a7) MUX -0.506 Volts -1.998 clocks
CCD 2 bias 12 ADC 2048 ( 800) MUX -0.001 Volts 0.000 Ground
CCD 2 bias 13 ADC 2048 ( 800) MUX -0.001 Volts 0.000 Ground
CCD 2 bias 14 ADC 2048 ( 800) MUX -0.001 Volts 0.000 Ground
CCD 2 bias 15 ADC 2048 ( 800) MUX -0.001 Volts 0.000 Ground
2 closed bias voltages were not within tolerance
Check to see if something is loading down the affected bias voltages
Low-rail clock voltages for clock gen 1
CLKGEN 1 clock 0 ADC 1703 ( 6a7) MUX -0.505 Volts -1.995
CLKGEN 1 clock 1 ADC 1702 ( 6a6) MUX -0.507 Volts -2.001
CLKGEN 1 clock 2 ADC 1702 ( 6a6) MUX -0.507 Volts -2.001
CLKGEN 1 clock 3 ADC 1219 ( 4c3) MUX -1.214 Volts -4.794
CLKGEN 1 clock 4 ADC 1270 ( 4f6) MUX -1.139 Volts -4.499
CLKGEN 1 clock 5 ADC 1270 ( 4f6) MUX -1.139 Volts -4.499
CLKGEN 1 clock 6 ADC 1270 ( 4f6) MUX -1.139 Volts -4.499
CLKGEN 1 clock 7 ADC 1270 ( 4f6) MUX -1.139 Volts -4.499
CLKGEN 1 clock 8 ADC 1270 ( 4f6) MUX -1.139 Volts -4.499
CLKGEN 1 clock 9 ADC 1218 ( 4c2) MUX -1.215 Volts -4.800
CLKGEN 1 clock 10 ADC 890 ( 37a) MUX -1.695 Volts -6.697
CLKGEN 1 clock 11 ADC 752 ( 2f0) MUX -1.898 Volts -7.495
CLKGEN 1 clock 12 ADC 1702 ( 6a6) MUX -0.507 Volts -2.001
CLKGEN 1 clock 13 ADC 1702 ( 6a6) MUX -0.507 Volts -2.001
CLKGEN 1 clock 14 ADC 1702 ( 6a6) MUX -0.507 Volts -2.001
CLKGEN 1 clock 15 ADC 1184 ( 4a0) MUX -1.265 Volts -4.997
CLKGEN 1 clock 16 ADC 1269 ( 4f5) MUX -1.141 Volts -4.505
CLKGEN 1 clock 17 ADC 1270 ( 4f6) MUX -1.139 Volts -4.499
CLKGEN 1 clock 18 ADC 1270 ( 4f6) MUX -1.139 Volts -4.499
CLKGEN 1 clock 19 ADC 1270 ( 4f6) MUX -1.139 Volts -4.499
CLKGEN 1 clock 20 ADC 1270 ( 4f6) MUX -1.139 Volts -4.499
CLKGEN 1 clock 21 ADC 1184 ( 4a0) MUX -1.265 Volts -4.997
CLKGEN 1 clock 22 ADC 890 ( 37a) MUX -1.695 Volts -6.697
CLKGEN 1 clock 23 ADC 891 ( 37b) MUX -1.694 Volts -6.691
High-rail clock voltages for clock gen 1
CLKGEN 1 clock 0 ADC 2844 ( b1c) MUX 1.165 Volts 4.604
CLKGEN 1 clock 1 ADC 2844 ( b1c) MUX 1.165 Volts 4.604
CLKGEN 1 clock 2 ADC 2844 ( b1c) MUX 1.165 Volts 4.604
CLKGEN 1 clock 3 ADC 2913 ( b61) MUX 1.266 Volts 5.003
CLKGEN 1 clock 4 ADC 3085 ( c0d) MUX 1.518 Volts 5.997
CLKGEN 1 clock 5 ADC 3085 ( c0d) MUX 1.518 Volts 5.997
CLKGEN 1 clock 6 ADC 3085 ( c0d) MUX 1.518 Volts 5.997
CLKGEN 1 clock 7 ADC 3085 ( c0d) MUX 1.518 Volts 5.997
CLKGEN 1 clock 8 ADC 3224 ( c98) MUX 1.722 Volts 6.801
CLKGEN 1 clock 9 ADC 2913 ( b61) MUX 1.266 Volts 5.003
CLKGEN 1 clock 10 ADC 2221 ( 8ad) MUX 0.253 Volts 1.001
CLKGEN 1 clock 11 ADC 2221 ( 8ad) MUX 0.253 Volts 1.001
CLKGEN 1 clock 12 ADC 2844 ( b1c) MUX 1.165 Volts 4.604
CLKGEN 1 clock 13 ADC 2844 ( b1c) MUX 1.165 Volts 4.604
CLKGEN 1 clock 14 ADC 2844 ( b1c) MUX 1.165 Volts 4.604
CLKGEN 1 clock 15 ADC 2913 ( b61) MUX 1.266 Volts 5.003
CLKGEN 1 clock 16 ADC 3172 ( c64) MUX 1.646 Volts 6.500
CLKGEN 1 clock 17 ADC 3172 ( c64) MUX 1.646 Volts 6.500
CLKGEN 1 clock 18 ADC 3172 ( c64) MUX 1.646 Volts 6.500
CLKGEN 1 clock 19 ADC 3172 ( c64) MUX 1.646 Volts 6.500
CLKGEN 1 clock 20 ADC 3172 ( c64) MUX 1.646 Volts 6.500
CLKGEN 1 clock 21 ADC 2913 ( b61) MUX 1.266 Volts 5.003
CLKGEN 1 clock 22 ADC 2221 ( 8ad) MUX 0.253 Volts 1.001
CLKGEN 1 clock 23 ADC 2221 ( 8ad) MUX 0.253 Volts 1.001
Closed clock voltages are all within tolerance
Now commanding shutter closed
+5v readback raw ADC reading = 3428 volts= 5.046331 prior to clocking
+15v readback raw ADC reading = 3514 voltage = 16.485247 prior to clocking
-15v readback raw ADC reading = 591 voltage = -16.384041 prior to clocking
+30v readback raw ADC reading = 3289 volts = 34.819450 prior to clocking
Sending IDL command to TIMING board
CCD clocks are now running in idling mode
value = 0 = 0x0
-> i NAME ENTRY TID PRI STATUS PC SP ERRNO DELAY ---------- ------------ -------- --- ---------- -------- -------- ------- ----- tExcTask excTask 3dfe1b8 0 PEND 185940 3dfe0e0 0 0 tLogTask logTask 3dfb840 0 PEND 185940 3dfb778 0 0 tShell shell 3de4d28 1 READY 157924 3de49b0 c0002 0 tRlogind rlogind 3df3770 2 PEND 153f60 3df33b0 0 0 tTelnetd telnetd 3df1848 2 PEND 153f60 3df16e8 0 0 tWdbTask 14c1c4 3de6f30 3 PEND 153f60 3de6d98 0 0 tNetTask netTask 3df6c38 50 PEND 153f60 3df6b88 0 0 tTftpdTask tftpdTask 3deebf0 55 PEND 153f60 3dee428 0 0 ccdClock ccdClock 3c23530 90 DELAY 156ed8 3c23470 3d0002 1 tPortmapd portmapd 3df02b8 100 PEND 153f60 3df0148 16 0 MLOG_STDOUTstart_mlog_s 3c54680 100 PEND 185940 3c54380 0 0 cserv cserv 3c3bdd8 100 PEND 153f60 3c3bbc0 0 0 responder responder 3b274f0 100 PEND 185940 3b263d8 0 0 rccd rccd 3c151b8 150 PEND+T 153f60 3c15018 3d0004 45 value = 0 = 0x0
-> < broadcast
taskSpawn("broad_mon", 110, 0x19, 10000, broadcast_mon, "/vx/lrisredm/dsp")
value = 61859488 = 0x3afe6a0
-> < dewartemp
taskSpawn("dewar_temp", 160, 0x19, 20000, control_dewar_temperature, "", 5)
value = 61848968 = 0x3afbd88
i NAME ENTRY TID PRI STATUS PC SP ERRNO DELAY ---------- ------------ -------- --- ---------- -------- -------- ------- ----- tExcTask excTask 3dfe1b8 0 PEND 185940 3dfe0e0 0 0 tLogTask logTask 3dfb840 0 PEND 185940 3dfb778 0 0 tShell shell 3de4d28 1 READY 157924 3de49b0 c0002 0 tRlogind rlogind 3df3770 2 PEND 153f60 3df33b0 0 0 tTelnetd telnetd 3df1848 2 PEND 153f60 3df16e8 0 0 tWdbTask 14c1c4 3de6f30 3 PEND 153f60 3de6d98 0 0 tNetTask netTask 3df6c38 50 PEND 153f60 3df6b88 0 0 tTftpdTask tftpdTask 3deebf0 55 PEND 153f60 3dee428 0 0 ccdClock ccdClock 3c23530 90 DELAY 156ed8 3c23470 3d0002 1 tPortmapd portmapd 3df02b8 100 PEND 153f60 3df0148 16 0 MLOG_STDOUTstart_mlog_s 3c54680 100 PEND 185940 3c54380 0 0 cserv cserv 3c3bdd8 100 PEND 153f60 3c3bbc0 0 0 responder responder 3b274f0 100 PEND 185940 3b263d8 0 0 broad_mon broadcast_mo 3afe6a0 110 DELAY 156ed8 3afe5e0 0 47 rccd rccd 3c151b8 150 PEND+T 153f60 3c15018 3d0004 17 dewar_temp control_dewa 3afbd88 160 DELAY 156ed8 3afbc30 3d0001 26 value = 0 = 0x0
Press any key to stop auto-boot...
0
auto-booting...
boot device : dc
processor number : 0
host name : lris-red-p
file name : /usr/local/ucolick/vx/mv2304/lrisredm/vme/hosts/vxWorks
inet on ethernet (e) : 192.9.200.21:ffffff00
host inet (h) : 192.9.200.25
user (u) : lriscrates
flags (f) : 0x2
target name (tn) : biden
startup script (s) : /usr/local/ucolick/vx/mv2304/lrisredm/vme/hosts/lrisredm
Attaching network interface dc0... done.
Attaching network interface lo0... done.
Loading... 777984
Starting at 0x100000...
Attaching network interface dc0... done.
Attaching network interface lo0... done.
Loading symbol table from lris-red-p:/usr/local/ucolick/vx/mv2304/lrisredm/vme/hosts/vxWorks.sym ...done
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]]]]]]]]]]] ]]]] ]]]]]]]]]] ]] ]]]] (R)
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]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]
]]]]]]]]]]]]]]]]]]]]]]]]]]]]] Development System
]]]]]]]]]]]]]]]]]]]]]]]]]]]]
]]]]]]]]]]]]]]]]]]]]]]]]]]] VxWorks version 5.3.1
]]]]]]]]]]]]]]]]]]]]]]]]]] KERNEL: WIND version 2.5
]]]]]]]]]]]]]]]]]]]]]]]]] Copyright Wind River Systems, Inc., 1984-1997
CPU: Motorola MVME2300 - MPC 604e. Processor #0.
Memory Size: 0x4000000. BSP version 1.1/4.
WDB: Ready.
Executing startup script /usr/local/ucolick/vx/mv2304/lrisredm/vme/hosts/lrisredm ...
iam "lriscrates"
value = 0 = 0x0
hostShow
hostname inet address aliases
-------- ------------ -------
biden 192.9.200.21
localhost 127.0.0.1
lris-red-p 192.9.200.25
value = 0 = 0x0
routeShow
ROUTE NET TABLE
destination gateway flags Refcnt Use Interface
------------------------------------------------------------------------
192.9.200.0 192.9.200.21 1 0 113 dc0
------------------------------------------------------------------------
ROUTE HOST TABLE
destination gateway flags Refcnt Use Interface
------------------------------------------------------------------------
127.0.0.1 127.0.0.1 5 1 0 lo0
------------------------------------------------------------------------
value = 73 = 0x49 = 'I'
nfsAuthUnixPrompt
machine name: lris-red-p user ID: 2001 group ID: 100 num of groups: 0 value = 0 = 0x0
nfsMount "lris-red-p","/usr/local/ucolick/vx","/vx"
value = 0 = 0x0
nfsDevShow
device name file system
----------- -----------
/vx lris-red-p:/usr/local/ucolick/vx
value = 0 = 0x0
cd "/vx/mv2304/lrisredm/vme"
value = 0 = 0x0
ld < universeDma.o
value = 64877408 = 0x3ddf360 = univDmaStat + 0x68
ld < dma_mast_ctl_test.o
value = 64879200 = 0x3ddfa60 = univDmaStat + 0x768
cd "/vx/mv2304/lrisredm/vme/hosts"
value = 0 = 0x0
Done executing startup script /usr/local/ucolick/vx/mv2304/lrisredm/vme/hosts/lrisredm
->
-> < logo sysVmeDmaShow() ADDRESSES OF UNIVERSE DMA REGISTERS PCI_CSR=> 0xfd050004 LMISC => 0xfd050184 L_CMDERR=> 0xfd05018c LAERR => 0xfd050190 DCTL => 0xfd050200 DTBC => 0xfd050204 DLA => 0xfd050208 DVA => 0xfd050210 DCPP => 0xfd050218 DGCS => 0xfd050220 D_LLUE => 0xfd050224 LINT_EN => 0xfd050300 LINT_STAT => 0xfd050304 LINT_MAP0 => 0xfd050308 LINT_MAP1 => 0xfd05030c VINT_EN => 0xfd050310 VINT_STAT => 0xfd050314 MAST_CTL => 0xfd050400 MISC_CTL => 0xfd050404 MISC_STAT => 0xfd050408 V_AMERR => 0xfd050f88 VAERR => 0xfd050f8c VCSR_CLR => 0xfd050ff4 CURRENT STATE OF UNIVERSE DMA REGISTERS PCI_CSR=> 0x2000006 LMISC => 0x10000000 L_CMDERR=> 0x70000000 LAERR => 0x3dae0c0 DCTL => 0x0 DTBC => 0x0 DLA => 0x0 DVA => 0x0 DCPP => 0x0 DGCS => 0x0 D_LLUE => 0x0 LINT_EN => 0x0 LINT_STAT => 0x0 LINT_MAP0 => 0x0 LINT_MAP1 => 0x0 VINT_EN => 0x0 VINT_STAT => 0xf0 MAST_CTL => 0x5c00000 MISC_CTL => 0x52060000 MISC_STAT => 0x40260000 V_AMERR => 0x24000000 VAERR => 0x1eeff00c VCSR_CLR => 0x0 value = 17 = 0x11 cd "/vx/mv2304/optical/vme/lzo" value = 0 = 0x0 ld0xfd050004 LMISC => 0xfd050184 L_CMDERR=> 0xfd05018c LAERR => 0xfd050190 DCTL => 0xfd050200 DTBC => 0xfd050204 DLA => 0xfd050208 DVA => 0xfd050210 DCPP => 0xfd050218 DGCS => 0xfd050220 D_LLUE => 0xfd050224 LINT_EN => 0xfd050300 LINT_STAT => 0xfd050304 LINT_MAP0 => 0xfd050308 LINT_MAP1 => 0xfd05030c VINT_EN => 0xfd050310 VINT_STAT => 0xfd050314 MAST_CTL => 0xfd050400 MISC_CTL => 0xfd050404 MISC_STAT => 0xfd050408 V_AMERR => 0xfd050f88 VAERR => 0xfd050f8c VCSR_CLR => 0xfd050ff4 CURRENT STATE OF UNIVERSE DMA REGISTERS PCI_CSR=> 0x2000006 LMISC => 0x10000000 L_CMDERR=> 0x70000000 LAERR => 0x3dae0c0 DCTL => 0x0 DTBC => 0x0 DLA => 0x0 DVA => 0x0 DCPP => 0x0 DGCS => 0x0 D_LLUE => 0x0 LINT_EN => 0x0 LINT_STAT => 0x0 LINT_MAP0 => 0x0 LINT_MAP1 => 0x0 VINT_EN => 0x0 VINT_STAT => 0xf0 MAST_CTL => 0x5c00000 MISC_CTL => 0x52060000 MISC_STAT => 0x40260000 V_AMERR => 0x24000000 VAERR => 0x1eeff00c VCSR_CLR => 0x0 value = 17 = 0x11 pipeDrv value = 0 = 0x0 set_mlog_lfile( "/vx/lrisredm/logs/mlog_log") "mlog_composite.c",line 1637: 0: New mlog logfile set. value = 0 = 0x0 make_response_pipe value = 0 = 0x0 make_mlog_pipes value = 0 = 0x0 startup_mlog ("STDOUT") value = 0 = 0x0 set_mlog_dest ("DBG W0 W1 W2 E0 E1 E2 ST RPT", "DEL", "STDERR") value = 0 = 0x0 set_mlog_dest ("W0 W1 W2 E0 E1 E2 ST RPT", "ADD", "STDOUT") value = 0 = 0x0 crate_global_init value = 0 = 0x0 sysVmeDmaShow() ADDRESSES OF UNIVERSE DMA REGISTERS PCI_CSR=> 0xfd050004 LMISC => 0xfd050184 L_CMDERR=> 0xfd05018c LAERR => 0xfd050190 DCTL => 0xfd050200 DTBC => 0xfd050204 DLA => 0xfd050208 DVA => 0xfd050210 DCPP => 0xfd050218 DGCS => 0xfd050220 D_LLUE => 0xfd050224 LINT_EN => 0xfd050300 LINT_STAT => 0xfd050304 LINT_MAP0 => 0xfd050308 LINT_MAP1 => 0xfd05030c VINT_EN => 0xfd050310 VINT_STAT => 0xfd050314 MAST_CTL => 0xfd050400 MISC_CTL => 0xfd050404 MISC_STAT => 0xfd050408 V_AMERR => 0xfd050f88 VAERR => 0xfd050f8c VCSR_CLR => 0xfd050ff4 CURRENT STATE OF UNIVERSE DMA REGISTERS PCI_CSR=> 0x2000006 LMISC => 0x10000000 L_CMDERR=> 0x70000000 LAERR => 0x3dae0c0 DCTL => 0x0 DTBC => 0x0 DLA => 0x0 DVA => 0x0 DCPP => 0x0 DGCS => 0x0 D_LLUE => 0x0 LINT_EN => 0x0 LINT_STAT => 0x0 LINT_MAP0 => 0x0 LINT_MAP1 => 0x0 VINT_EN => 0x0 VINT_STAT => 0xf0 MAST_CTL => 0x5c00000 MISC_CTL => 0x52060000 MISC_STAT => 0x40260000 V_AMERR => 0x24000000 VAERR => 0x1eeffffc VCSR_CLR => 0x0 value = 17 = 0x11 sysVmeDmaSlaves() ADDRESSES OF UNIVERSE SLAVE CONTROL REGISTERS LSI0_CTL=> 0xfd050100 LSI1_CTL=> 0xfd050114 LSI2_CTL=> 0xfd050128 LSI3_CTL=> 0xfd05013c SCYC_CTL=> 0xfd050170 VSI0_CTL=> 0xfd050f00 VSI1_CTL=> 0xfd050f14 VSI2_CTL=> 0xfd050f28 VSI3_CTL=> 0xfd050f3c VRAI_CTL=> 0xfd050f70 VCSR_CTL=> 0xfd050f80 CURRENT STATE OF UNIVERSE SLAVE CONTROL REGISTERS LSI0_CTL=> 0xc0c20000 LSI1_CTL=> 0xc0c20000 LSI2_CTL=> 0xc0c10000 LSI3_CTL=> 0xc0c00000 SCYC_CTL=> 0x0 VSI0_CTL=> 0x80f20001 VSI1_CTL=> 0xa0f20080 VSI2_CTL=> 0x0 VSI3_CTL=> 0x0 VRAI_CTL=> 0x0 VCSR_CTL=> 0x0 VSI0_CTL=> 0x0 VSI1_CTL=> 0x0 VSI2_CTL=> 0x0 VSI3_CTL=> 0x0 value = 15 = 0xf sysVmeDmaInit() value = 0 = 0x0 sysVmeDmaShow() ADDRESSES OF UNIVERSE DMA REGISTERS PCI_CSR=> 0xfd050004 LMISC => 0xfd050184 L_CMDERR=> 0xfd05018c LAERR => 0xfd050190 DCTL => 0xfd050200 DTBC => 0xfd050204 DLA => 0xfd050208 DVA => 0xfd050210 DCPP => 0xfd050218 DGCS => 0xfd050220 D_LLUE => 0xfd050224 LINT_EN => 0xfd050300 LINT_STAT => 0xfd050304 LINT_MAP0 => 0xfd050308 LINT_MAP1 => 0xfd05030c VINT_EN => 0xfd050310 VINT_STAT => 0xfd050314 MAST_CTL => 0xfd050400 MISC_CTL => 0xfd050404 MISC_STAT => 0xfd050408 V_AMERR => 0xfd050f88 VAERR => 0xfd050f8c VCSR_CLR => 0xfd050ff4 CURRENT STATE OF UNIVERSE DMA REGISTERS PCI_CSR=> 0x2000006 LMISC => 0x10000000 L_CMDERR=> 0x70000000 LAERR => 0x3dae0c0 DCTL => 0x0 DTBC => 0x0 DLA => 0x0 DVA => 0x0 DCPP => 0x0 DGCS => 0x0 D_LLUE => 0x0 LINT_EN => 0x100 LINT_STAT => 0x0 LINT_MAP0 => 0x0 LINT_MAP1 => 0x0 VINT_EN => 0x0 VINT_STAT => 0xf0 MAST_CTL => 0x5c00000 MISC_CTL => 0x52060000 MISC_STAT => 0x40260000 V_AMERR => 0x24000000 VAERR => 0x1eeffffc VCSR_CLR => 0x0 value = 17 = 0x11 taskDelay(60) value = 0 = 0x0 sysVmeDmaShow() ADDRESSES OF UNIVERSE DMA REGISTERS PCI_CSR=> 0xfd050004 LMISC => 0xfd050184 L_CMDERR=> 0xfd05018c LAERR => 0xfd050190 DCTL => 0xfd050200 DTBC => 0xfd050204 DLA => 0xfd050208 DVA => 0xfd050210 DCPP => 0xfd050218 DGCS => 0xfd050220 D_LLUE => 0xfd050224 LINT_EN => 0xfd050300 LINT_STAT => 0xfd050304 LINT_MAP0 => 0xfd050308 LINT_MAP1 => 0xfd05030c VINT_EN => 0xfd050310 VINT_STAT => 0xfd050314 MAST_CTL => 0xfd050400 MISC_CTL => 0xfd050404 MISC_STAT => 0xfd050408 V_AMERR => 0xfd050f88 VAERR => 0xfd050f8c VCSR_CLR => 0xfd050ff4 CURRENT STATE OF UNIVERSE DMA REGISTERS PCI_CSR=> 0x2000006 LMISC => 0x10000000 L_CMDERR=> 0x70000000 LAERR => 0x3dae0c0 DCTL => 0x0 DTBC => 0x0 DLA => 0x0 DVA => 0x0 DCPP => 0x0 DGCS => 0x0 D_LLUE => 0x0 LINT_EN => 0x100 LINT_STAT => 0x0 LINT_MAP0 => 0x0 LINT_MAP1 => 0x0 VINT_EN => 0x0 VINT_STAT => 0xf0 MAST_CTL => 0x5c00000 MISC_CTL => 0x52060000 MISC_STAT => 0x40260000 V_AMERR => 0x24000000 VAERR => 0x1eeffffc VCSR_CLR => 0x0 value = 17 = 0x11 sysVmeDmaShow() ADDRESSES OF UNIVERSE DMA REGISTERS PCI_CSR=> 0xfd050004 LMISC => 0xfd050184 L_CMDERR=> 0xfd05018c LAERR => 0xfd050190 DCTL => 0xfd050200 DTBC => 0xfd050204 DLA => 0xfd050208 DVA => 0xfd050210 DCPP => 0xfd050218 DGCS => 0xfd050220 D_LLUE => 0xfd050224 LINT_EN => 0xfd050300 LINT_STAT => 0xfd050304 LINT_MAP0 => 0xfd050308 LINT_MAP1 => 0xfd05030c VINT_EN => 0xfd050310 VINT_STAT => 0xfd050314 MAST_CTL => 0xfd050400 MISC_CTL => 0xfd050404 MISC_STAT => 0xfd050408 V_AMERR => 0xfd050f88 VAERR => 0xfd050f8c VCSR_CLR => 0xfd050ff4 CURRENT STATE OF UNIVERSE DMA REGISTERS PCI_CSR=> 0x2000006 LMISC => 0x10000000 L_CMDERR=> 0x70000000 LAERR => 0x3dae0c0 DCTL => 0x0 DTBC => 0x0 DLA => 0x0 DVA => 0x0 DCPP => 0x0 DGCS => 0x0 D_LLUE => 0x0 LINT_EN => 0x100 LINT_STAT => 0x0 LINT_MAP0 => 0x0 LINT_MAP1 => 0x0 VINT_EN => 0x0 VINT_STAT => 0xf0 MAST_CTL => 0x5c00000 MISC_CTL => 0x52060000 MISC_STAT => 0x40260000 V_AMERR => 0x24000000 VAERR => 0x1eeffffc VCSR_CLR => 0x0 value = 17 = 0x11 taskSpawn("cserv",100,0x19,100000,cserv,"ldserv","/vx/lrisredm/logs/music_log") value = 63178880 = 0xtropen: our hos3c40880t = sysVmeDmaShow()biden ADDRESSES OF UNIVERSE DMA REGISTERS . PCI_CSR=> 0xtropen: remotefd050004 host = LMISC => 0xlris-redfd050184-p L_CMDERR=> 0x fd05018c LAERR => 0xstartprocfd050190: parameter hostname = DCTL => 0xlris-red-pfd050200 DTBC => 0xstartproc: gethostfd050204name returne d DLA => 0xfd050208biden DVA => 0x fd050210 DCPP => 0xstartprofd050218c: SOCK_CONN ECT succeeded; msga DGCS => 0xddr =fd050220 D_LLUE => 0x16778230fd050224 LINT_EN => 0xfd050300 LINT_STAT => 0xfd050304 LINT_MAP0 => 0xfd050308 LINT_MAP1 => 0xfd05030c VINT_EN => 0xfd050310 VINT_STAT => 0xfd050314 MAST_CTL => 0xfd050400 MISC_CTL => 0xfd050404 MISC_STAT => 0xfd050408 V_AMERR => 0xfd050f88 VAERR => 0xfd050f8c VCSR_CLR => 0xfd050ff4 CURRENT STATE OF UNIVERSE DMA REGISTERS PCI_CSR=> 0x2000006 LMISC => 0x10000000 L_CMDERR=> 0x70000000 LAERR => 0x3dae0c0 DCTL => 0x0 DTBC => 0x0 DLA => 0x0 DVA => 0x0 DCPP => 0x0 DGCS => 0x0 D_LLUE => 0x0 LINT_EN => 0x100 LINT_STAT => 0x0 LINT_MAP0 => 0x0 LINT_MAP1 => 0x0 VINT_EN => 0x0 VINT_STAT => 0xf0 MAST_CTL => 0x5c00000 MISC_CTL => 0x52060000 MISC_STAT => 0x40260000 V_AMERR => 0x24000000 VAERR => 0x1eeffffc VCSR_CLR => 0x0 value = 17 = 0x11 taskSpawn("ccdClock",90,0x19,40000,ccdClock) value = 62960128 = 0x3c0b200 sysVmeDmaShow() ADDRESSES OF UNIVERSE DMA REGISTERS PCI_CSR=> 0xfd050004 LMISC => 0xfd050184 L_CMDERR=> 0xfd05018c LAERR => 0xfd050190 DCTL => 0xfd050200 DTBC => 0xfd050204 DLA => 0xfd050208 DVA => 0xfd050210 DCPP => 0xfd050218 DGCS => 0xfd050220 D_LLUE => 0xfd050224 LINT_EN => 0xfd050300 LINT_STAT => 0xfd050304 LINT_MAP0 => 0xfd050308 LINT_MAP1 => 0xfd05030c VINT_EN => 0xfd050310 VINT_STAT => 0xfd050314 MAST_CTL => 0xfd050400 MISC_CTL => 0xfd050404 MISC_STAT => 0xfd050408 V_AMERR => 0xfd050f88 VAERR => 0xfd050f8c VCSR_CLR => 0xfd050ff4 CURRENT STATE OF UNIVERSE DMA REGISTERS PCI_CSR=> 0x2000006 LMISC => 0x10000000 L_CMDERR=> 0x70000000 LAERR => 0x3dae0c0 DCTL => 0x0 DTBC => 0x0 DLA => 0x0 DVA => 0x0 DCPP => 0x0 DGCS => 0x0 D_LLUE => 0x0 LINT_EN => 0x100 LINT_STAT => 0x0 LINT_MAP0 => 0x0 LINT_MAP1 => 0x0 VINT_EN => 0x0 VINT_STAT => 0xf0 MAST_CTL => 0x5c00000 MISC_CTL => 0x52060000 MISC_STAT => 0x40260000 V_AMERR => 0x24000000 VAERR => 0x1eeffffc VCSR_CLR => 0x0 value = 17 = 0x11 taskDelay(3) value = 0 = 0x0 taskSpawn("rccd",150,0x19,900000,rccd,"/vx/mv2304/lrisredm/vme/hosts/lrisredm.conf") value = 62919608 = 0xConfiguration f3c013b8ile read, retu rn value is taskDelay(15)0 We have 1 controllers Allocated socket 18 Broadcasts enabled Socket successfully assigned Got network configuration Broadcast message sent on dc0 Broadcast not sent on lo0 All timeouts cleared Using 192.9.200.25 as my server value = 0 = 0x0 sysVmeDmaShow() ADDRESSES OF UNIVERSE DMA REGISTERS PCI_CSR=> 0xfd050004 LMISC => 0xfd050184 L_CMDERR=> 0xfd05018c LAERR => 0xfd050190 DCTL => 0xfd050200 DTBC => 0xfd050204 DLA => 0xfd050208 DVA => 0xfd050210 DCPP => 0xfd050218 DGCS => 0xfd050220 D_LLUE => 0xfd050224 LINT_EN => 0xfd050300 LINT_STAT => 0xfd050304 LINT_MAP0 => 0xfd050308 LINT_MAP1 => 0xfd05030c VINT_EN => 0xfd050310 VINT_STAT => 0xfd050314 MAST_CTL => 0xfd050400 MISC_CTL => 0xfd050404 MISC_STAT => 0xfd050408 V_AMERR => 0xfd050f88 VAERR => 0xfd050f8c VCSR_CLR => 0xfd050ff4 CURRENT STATE OF UNIVERSE DMA REGISTERS PCI_CSR=> 0x2000006 LMISC => 0x10000000 L_CMDERR=> 0x70000000 LAERR => 0x3dae0c0 DCTL => 0x0 DTBC => 0x0 DLA => 0x0 DVA => 0x0 DCPP => 0x0 DGCS => 0x0 D_LLUE => 0x0 LINT_EN => 0x100 LINT_STAT => 0x0 LINT_MAP0 => 0x0 LINT_MAP1 => 0x0 VINT_EN => 0x0 VINT_STAT => 0xf0 MAST_CTL => 0x5c00000 MISC_CTL => 0x52060000 MISC_STAT => 0x40260000 V_AMERR => 0x24000000 VAERR => 0x1eeffffc VCSR_CLR => 0x0 value = 17 = 0x11 taskDelay(15) value = 0 = 0x0 sysVmeDmaShow() ADDRESSES OF UNIVERSE DMA REGISTERS PCI_CSR=> 0xfd050004 LMISC => 0xfd050184 L_CMDERR=> 0xfd05018c LAERR => 0xfd050190 DCTL => 0xfd050200 DTBC => 0xfd050204 DLA => 0xfd050208 DVA => 0xfd050210 DCPP => 0xfd050218 DGCS => 0xfd050220 D_LLUE => 0xfd050224 LINT_EN => 0xfd050300 LINT_STAT => 0xfd050304 LINT_MAP0 => 0xfd050308 LINT_MAP1 => 0xfd05030c VINT_EN => 0xfd050310 VINT_STAT => 0xfd050314 MAST_CTL => 0xfd050400 MISC_CTL => 0xfd050404 MISC_STAT => 0xfd050408 V_AMERR => 0xfd050f88 VAERR => 0xfd050f8c VCSR_CLR => 0xfd050ff4 CURRENT STATE OF UNIVERSE DMA REGISTERS PCI_CSR=> 0x2000006 LMISC => 0x10000000 L_CMDERR=> 0x70000000 LAERR => 0x3dae0c0 DCTL => 0x0 DTBC => 0x0 DLA => 0x0 DVA => 0x0 DCPP => 0x0 DGCS => 0x0 D_LLUE => 0x0 LINT_EN => 0x100 LINT_STAT => 0x0 LINT_MAP0 => 0x0 LINT_MAP1 => 0x0 VINT_EN => 0x0 VINT_STAT => 0xf0 MAST_CTL => 0x5c00000 MISC_CTL => 0x52060000 MISC_STAT => 0x40260000 V_AMERR => 0x24000000 VAERR => 0x1eeffffc VCSR_CLR => 0x0 value = 17 = 0x11 cd "/vx/mv2304/lrisredm/vme/vmeinf/lick" value = 0 = 0x0 ld < tim_download.o value = 63975992 = 0x3d03238 ld < tim_verify.o value = 64045368 = 0x3d14138 = sline + 0x3a8 ld < vme_download.o value = 64044808 = 0x3d13f08 = sline + 0x178 ld < vme_verify.o value = 63983592 = 0x3d04fe8 = dsp_don + 0x7c8 ld < util_download.o value = 63983152 = 0x3d04e30 = sline + 0x5b8 ld < util_verify.o value = 63982592 = 0x3d04c00 = sline + 0x388 ld < startup.o value = 63987816 = 0x3d06068 = dsp_don + 0x320 cd "/vx/mv2304/lrisredm/vme/ldserv" value = 0 = 0x0 ld 0xfd050004 LMISC => 0xfd050184 L_CMDERR=> 0xfd05018c LAERR => 0xfd050190 DCTL => 0xfd050200 DTBC => 0xfd050204 DLA => 0xfd050208 DVA => 0xfd050210 DCPP => 0xfd050218 DGCS => 0xfd050220 D_LLUE => 0xfd050224 LINT_EN => 0xfd050300 LINT_STAT => 0xfd050304 LINT_MAP0 => 0xfd050308 LINT_MAP1 => 0xfd05030c VINT_EN => 0xfd050310 VINT_STAT => 0xfd050314 MAST_CTL => 0xfd050400 MISC_CTL => 0xfd050404 MISC_STAT => 0xfd050408 V_AMERR => 0xfd050f88 VAERR => 0xfd050f8c VCSR_CLR => 0xfd050ff4 CURRENT STATE OF UNIVERSE DMA REGISTERS PCI_CSR=> 0x2000006 LMISC => 0x10000000 L_CMDERR=> 0x70000000 LAERR => 0x3dae0c0 DCTL => 0x0 DTBC => 0x0 DLA => 0x0 DVA => 0x0 DCPP => 0x0 DGCS => 0x0 D_LLUE => 0x0 LINT_EN => 0x100 LINT_STAT => 0x0 LINT_MAP0 => 0x0 LINT_MAP1 => 0x0 VINT_EN => 0x0 VINT_STAT => 0xf0 MAST_CTL => 0x5c00000 MISC_CTL => 0x52060000 MISC_STAT => 0x40260000 V_AMERR => 0x24000000 VAERR => 0x1eeffffc VCSR_CLR => 0x0 value = 17 = 0x11 sysVmeDmaSet(4,1) value = 0 = 0x0 sysVmeDmaShow() ADDRESSES OF UNIVERSE DMA REGISTERS PCI_CSR=> 0xfd050004 LMISC => 0xfd050184 L_CMDERR=> 0xfd05018c LAERR => 0xfd050190 DCTL => 0xfd050200 DTBC => 0xfd050204 DLA => 0xfd050208 DVA => 0xfd050210 DCPP => 0xfd050218 DGCS => 0xfd050220 D_LLUE => 0xfd050224 LINT_EN => 0xfd050300 LINT_STAT => 0xfd050304 LINT_MAP0 => 0xfd050308 LINT_MAP1 => 0xfd05030c VINT_EN => 0xfd050310 VINT_STAT => 0xfd050314 MAST_CTL => 0xfd050400 MISC_CTL => 0xfd050404 MISC_STAT => 0xfd050408 V_AMERR => 0xfd050f88 VAERR => 0xfd050f8c VCSR_CLR => 0xfd050ff4 CURRENT STATE OF UNIVERSE DMA REGISTERS PCI_CSR=> 0x2000006 LMISC => 0x10000000 L_CMDERR=> 0x70000000 LAERR => 0x3dae0c0 DCTL => 0x0 DTBC => 0x0 DLA => 0x0 DVA => 0x0 DCPP => 0x0 DGCS => 0x0 D_LLUE => 0x0 LINT_EN => 0x100 LINT_STAT => 0x0 LINT_MAP0 => 0x0 LINT_MAP1 => 0x0 VINT_EN => 0x0 VINT_STAT => 0xf0 MAST_CTL => 0x5c00000 MISC_CTL => 0x52060000 MISC_STAT => 0x40260000 V_AMERR => 0x24000000 VAERR => 0x1eeffffc VCSR_CLR => 0x0 value = 17 = 0x11 sysVmeDmaSet(11,2) value = 0 = 0x0 sysVmeDmaShow() ADDRESSES OF UNIVERSE DMA REGISTERS PCI_CSR=> 0xfd050004 LMISC => 0xfd050184 L_CMDERR=> 0xfd05018c LAERR => 0xfd050190 DCTL => 0xfd050200 DTBC => 0xfd050204 DLA => 0xfd050208 DVA => 0xfd050210 DCPP => 0xfd050218 DGCS => 0xfd050220 D_LLUE => 0xfd050224 LINT_EN => 0xfd050300 LINT_STAT => 0xfd050304 LINT_MAP0 => 0xfd050308 LINT_MAP1 => 0xfd05030c VINT_EN => 0xfd050310 VINT_STAT => 0xfd050314 MAST_CTL => 0xfd050400 MISC_CTL => 0xfd050404 MISC_STAT => 0xfd050408 V_AMERR => 0xfd050f88 VAERR => 0xfd050f8c VCSR_CLR => 0xfd050ff4 CURRENT STATE OF UNIVERSE DMA REGISTERS PCI_CSR=> 0x2000006 LMISC => 0x10000000 L_CMDERR=> 0x70000000 LAERR => 0x3dae0c0 DCTL => 0x0 DTBC => 0x0 DLA => 0x0 DVA => 0x0 DCPP => 0x0 DGCS => 0x0 D_LLUE => 0x0 LINT_EN => 0x100 LINT_STAT => 0x0 LINT_MAP0 => 0x0 LINT_MAP1 => 0x0 VINT_EN => 0x0 VINT_STAT => 0xf0 MAST_CTL => 0x5c00000 MISC_CTL => 0x52060000 MISC_STAT => 0x40260000 V_AMERR => 0x24000000 VAERR => 0x1eeffffc VCSR_CLR => 0x0 value = 17 = 0x11 sysVmeDmaSet(12,5) value = 0 = 0x0 sysVmeDmaShow() ADDRESSES OF UNIVERSE DMA REGISTERS PCI_CSR=> 0xfd050004 LMISC => 0xfd050184 L_CMDERR=> 0xfd05018c LAERR => 0xfd050190 DCTL => 0xfd050200 DTBC => 0xfd050204 DLA => 0xfd050208 DVA => 0xfd050210 DCPP => 0xfd050218 DGCS => 0xfd050220 D_LLUE => 0xfd050224 LINT_EN => 0xfd050300 LINT_STAT => 0xfd050304 LINT_MAP0 => 0xfd050308 LINT_MAP1 => 0xfd05030c VINT_EN => 0xfd050310 VINT_STAT => 0xfd050314 MAST_CTL => 0xfd050400 MISC_CTL => 0xfd050404 MISC_STAT => 0xfd050408 V_AMERR => 0xfd050f88 VAERR => 0xfd050f8c VCSR_CLR => 0xfd050ff4 CURRENT STATE OF UNIVERSE DMA REGISTERS PCI_CSR=> 0x2000006 LMISC => 0x10000000 L_CMDERR=> 0x70000000 LAERR => 0x3dae0c0 DCTL => 0x0 DTBC => 0x0 DLA => 0x0 DVA => 0x0 DCPP => 0x0 DGCS => 0x0 D_LLUE => 0x0 LINT_EN => 0x100 LINT_STAT => 0x0 LINT_MAP0 => 0x0 LINT_MAP1 => 0x0 VINT_EN => 0x0 VINT_STAT => 0xf0 MAST_CTL => 0x5c00000 MISC_CTL => 0x52060000 MISC_STAT => 0x40260000 V_AMERR => 0x24000000 VAERR => 0x1eeffffc VCSR_CLR => 0x0 value = 17 = 0x11 sysVmeDmaSet(13,2) value = 0 = 0x0 sysVmeDmaShow() ADDRESSES OF UNIVERSE DMA REGISTERS PCI_CSR=> 0xfd050004 LMISC => 0xfd050184 L_CMDERR=> 0xfd05018c LAERR => 0xfd050190 DCTL => 0xfd050200 DTBC => 0xfd050204 DLA => 0xfd050208 DVA => 0xfd050210 DCPP => 0xfd050218 DGCS => 0xfd050220 D_LLUE => 0xfd050224 LINT_EN => 0xfd050300 LINT_STAT => 0xfd050304 LINT_MAP0 => 0xfd050308 LINT_MAP1 => 0xfd05030c VINT_EN => 0xfd050310 VINT_STAT => 0xfd050314 MAST_CTL => 0xfd050400 MISC_CTL => 0xfd050404 MISC_STAT => 0xfd050408 V_AMERR => 0xfd050f88 VAERR => 0xfd050f8c VCSR_CLR => 0xfd050ff4 CURRENT STATE OF UNIVERSE DMA REGISTERS PCI_CSR=> 0x2000006 LMISC => 0x10000000 L_CMDERR=> 0x70000000 LAERR => 0x3dae0c0 DCTL => 0x0 DTBC => 0x0 DLA => 0x0 DVA => 0x0 DCPP => 0x0 DGCS => 0x0 D_LLUE => 0x0 LINT_EN => 0x100 LINT_STAT => 0x0 LINT_MAP0 => 0x0 LINT_MAP1 => 0x0 VINT_EN => 0x0 VINT_STAT => 0xf0 MAST_CTL => 0x5c00000 MISC_CTL => 0x52060000 MISC_STAT => 0x40260000 V_AMERR => 0x24000000 VAERR => 0x1eeffffc VCSR_CLR => 0x0 value = 17 = 0x11 sysVmeDmaSet(14,3) value = 0 = 0x0 sysVmeDmaShow() ADDRESSES OF UNIVERSE DMA REGISTERS PCI_CSR=> 0xfd050004 LMISC => 0xfd050184 L_CMDERR=> 0xfd05018c LAERR => 0xfd050190 DCTL => 0xfd050200 DTBC => 0xfd050204 DLA => 0xfd050208 DVA => 0xfd050210 DCPP => 0xfd050218 DGCS => 0xfd050220 D_LLUE => 0xfd050224 LINT_EN => 0xfd050300 LINT_STAT => 0xfd050304 LINT_MAP0 => 0xfd050308 LINT_MAP1 => 0xfd05030c VINT_EN => 0xfd050310 VINT_STAT => 0xfd050314 MAST_CTL => 0xfd050400 MISC_CTL => 0xfd050404 MISC_STAT => 0xfd050408 V_AMERR => 0xfd050f88 VAERR => 0xfd050f8c VCSR_CLR => 0xfd050ff4 CURRENT STATE OF UNIVERSE DMA REGISTERS PCI_CSR=> 0x2000006 LMISC => 0x10000000 L_CMDERR=> 0x70000000 LAERR => 0x3dae0c0 DCTL => 0x0 DTBC => 0x0 DLA => 0x0 DVA => 0x0 DCPP => 0x0 DGCS => 0x0 D_LLUE => 0x0 LINT_EN => 0x100 LINT_STAT => 0x0 LINT_MAP0 => 0x0 LINT_MAP1 => 0x0 VINT_EN => 0x0 VINT_STAT => 0xf0 MAST_CTL => 0x5c00000 MISC_CTL => 0x52060000 MISC_STAT => 0x40260000 V_AMERR => 0x24000000 VAERR => 0x1eeffffc VCSR_CLR => 0x0 value = 17 = 0x11 taskDelay(60) value = 0 = 0x0 dma_mast_ctl_test 1,2 dma_mast_ctl: Request level ==>1 timeout ==>2 Initial settings: *UNIVERSE_MAST_CTL = 0x05c00000 *UNIVERSE_MISC_CTL = 0x52060000 *UNIVERSE_MISC_STAT= 0x40260000 *UNIVERSE_LMISC = 0x10000000 Proposed settings: *UNIVERSE_MAST_CTL = 0x03802000 *UNIVERSE_MISC_CTL = 0x14020000 *UNIVERSE_LMISC = 0x10000000 Updated settings: *UNIVERSE_MAST_CTL = 0x03802000 *UNIVERSE_MISC_CTL = 0x14020000 *UNIVERSE_MISC_STAT= 0x40260000 *UNIVERSE_LMISC = 0x10000000 value = 0 = 0x0 taskDelay(60) value = 0 = 0x0 sysVmeDmaShow() ADDRESSES OF UNIVERSE DMA REGISTERS PCI_CSR=> 0xfd050004 LMISC => 0xfd050184 L_CMDERR=> 0xfd05018c LAERR => 0xfd050190 DCTL => 0xfd050200 DTBC => 0xfd050204 DLA => 0xfd050208 DVA => 0xfd050210 DCPP => 0xfd050218 DGCS => 0xfd050220 D_LLUE => 0xfd050224 LINT_EN => 0xfd050300 LINT_STAT => 0xfd050304 LINT_MAP0 => 0xfd050308 LINT_MAP1 => 0xfd05030c VINT_EN => 0xfd050310 VINT_STAT => 0xfd050314 MAST_CTL => 0xfd050400 MISC_CTL => 0xfd050404 MISC_STAT => 0xfd050408 V_AMERR => 0xfd050f88 VAERR => 0xfd050f8c VCSR_CLR => 0xfd050ff4 CURRENT STATE OF UNIVERSE DMA REGISTERS PCI_CSR=> 0x2000006 LMISC => 0x10000000 L_CMDERR=> 0x70000000 LAERR => 0x3dae0c0 DCTL => 0x0 DTBC => 0x0 DLA => 0x0 DVA => 0x0 DCPP => 0x0 DGCS => 0x0 D_LLUE => 0x0 LINT_EN => 0x100 LINT_STAT => 0x0 LINT_MAP0 => 0x0 LINT_MAP1 => 0x0 VINT_EN => 0x0 VINT_STAT => 0xf0 MAST_CTL => 0x3802000 MISC_CTL => 0x14020000 MISC_STAT => 0x40260000 V_AMERR => 0x24000000 VAERR => 0x1eeffffc VCSR_CLR => 0x0 value = 17 = 0x11 sysUnivVERRClr() value = 33554438 = 0x2000006 sysVmeDmaShow() ADDRESSES OF UNIVERSE DMA REGISTERS PCI_CSR=> 0xfd050004 LMISC => 0xfd050184 L_CMDERR=> 0xfd05018c LAERR => 0xfd050190 DCTL => 0xfd050200 DTBC => 0xfd050204 DLA => 0xfd050208 DVA => 0xfd050210 DCPP => 0xfd050218 DGCS => 0xfd050220 D_LLUE => 0xfd050224 LINT_EN => 0xfd050300 LINT_STAT => 0xfd050304 LINT_MAP0 => 0xfd050308 LINT_MAP1 => 0xfd05030c VINT_EN => 0xfd050310 VINT_STAT => 0xfd050314 MAST_CTL => 0xfd050400 MISC_CTL => 0xfd050404 MISC_STAT => 0xfd050408 V_AMERR => 0xfd050f88 VAERR => 0xfd050f8c VCSR_CLR => 0xfd050ff4 CURRENT STATE OF UNIVERSE DMA REGISTERS PCI_CSR=> 0x2000006 LMISC => 0x10000000 L_CMDERR=> 0x70000000 LAERR => 0x3dae0c0 DCTL => 0x0 DTBC => 0x0 DLA => 0x0 DVA => 0x0 DCPP => 0x0 DGCS => 0x0 D_LLUE => 0x0 LINT_EN => 0x100 LINT_STAT => 0x0 LINT_MAP0 => 0x0 LINT_MAP1 => 0x0 VINT_EN => 0x0 VINT_STAT => 0xf0 MAST_CTL => 0x3802000 MISC_CTL => 0x14020000 MISC_STAT => 0x40260000 V_AMERR => 0x24000000 VAERR => 0x1eeffffc VCSR_CLR => 0x0 value = 17 = 0x11 get_ccd_dims( 0 ) get_ccd_dims: CCD has changed dimensions from 0 rows by 0 cols to 4096 rows by 2048 cols value = 1 = 0x1 ->