Background

This document descibes the procedure for turning on power to the DEIMOS Flexure Compensation System (FCS) CCD array after controller power has been restored at the chassis.

Procedure

  1. Log on to deimosserver using the dmoseng account.
  2. From the command line prompt in an xterm window, type the following command to start an FCS TIP session: 
    	start_crate f
  3. Issue the command 
    	reboot
    to bring the system up cleanly.
  4. Issue the command 
    	shutdown
    to verify that all systems are properly turned off.
  5. Issue the command 
    	< restart
    to invoke the restart script and verify that it completes without error.

Transcript

Below is a transcript of a successful completion of the DEIMOS FCS powerup sequence, with user input in blue and commentary in red. Please note that messages of the form Readccd task is still alive are generated asynchronously and have nothing to do with the restart script. Hence, they can appear at any point in the output and should not necessarily be expected to appear where they do in this sample log. 
[61] dmoseng@polo: start_crate fcs

First, reboot the controller:
-> reboot
...
Next, determine what tasks are running:
-> i

  NAME        ENTRY       TID    PRI   STATUS      PC       SP     ERRNO  DELAY
---------- ------------ -------- --- ---------- -------- -------- ------- -----
tExcTask   _excTask       ffed08   0 PEND          94950   ffeb20   d0003     0
tLogTask   _logTask       ffc3b0   0 PEND          94950   ffc1c8       0     0
tShell     _shell         fe8d58   1 READY         7f31c   fe86a0   30065     0
tRlogind   _rlogind       ff4b00   2 PEND          7bdfc   ff45a8       0     0
tTelnetd   _telnetd       ff2bf8   2 PEND          7bdfc   ff2900       0     0
tRlogOutTas_rlogOutTask   6ff168   2 READY         7bdfc   6fed88       0     0
tRlogInTask_rlogInTask    fdbac0   2 READY         7bd00   fdb678       0     0
tNetTask   _netTask       ff7fb8  50 READY         7cf64   ff7d00       0     0
tFtpdTask  _ftpdTask      ff0118  55 PEND          7bdfc   fefe10       0     0
ccdClock   _ccdClock      e3b528  90 READY         7e974   e3b3c0       0     0
tPortmapd  _portmapd      ff1688 100 PEND          7bdfc   ff1330      16     0
MLOG_STDOUT_start_mlog_   e6c638 100 PEND          94950   e6c0a8       0     0
cserv      _cserv         e53db0 100 PEND          7bdfc   e537a8       0     0
broad_mon  _broadcast_m   e159e8 100 DELAY         7e974   e15880  3d0001    18
responder  _responder     e130f0 100 PEND          94950   e11d88       0     0
rccd       _rccd          e2d1d0 150 PEND+T        7bdfc   e2ced8  3d0004    18
value = 0 = 0x0

Turn off system in an orderly manner:
-> shutdown
Have entered shutdown routine
Setting exit flags for monitor processes
Waiting for monitor processes to shutdown
Sending STP command to TIMING board
Sending LOR command to TIMING board
RD bias voltages have all been set to minimum voltage
Analog switches in dewar electronics commanded open
Analog switches in dewar electronics indicate open
Analog power has been commanded off
Now switch off main power at controller
value = 0 = 0x0

Next, determine what tasks are running:
-> i

  NAME        ENTRY       TID    PRI   STATUS      PC       SP     ERRNO  DELAY
---------- ------------ -------- --- ---------- -------- -------- ------- -----
tExcTask   _excTask       ffed08   0 PEND          94950   ffeb20   d0003     0
tLogTask   _logTask       ffc3b0   0 PEND          94950   ffc1c8       0     0
tShell     _shell         fe8d58   1 READY         7f31c   fe86a0   30065     0
tRlogind   _rlogind       ff4b00   2 PEND          7bdfc   ff45a8       0     0
tTelnetd   _telnetd       ff2bf8   2 PEND          7bdfc   ff2900       0     0
tRlogOutTas_rlogOutTask   6ff168   2 READY         7bdfc   6fed88       0     0
tRlogInTask_rlogInTask    fdbac0   2 READY         7bd00   fdb678       0     0
tNetTask   _netTask       ff7fb8  50 READY         7cf64   ff7d00       0     0
tFtpdTask  _ftpdTask      ff0118  55 PEND          7bdfc   fefe10       0     0
ccdClock   _ccdClock      e3b528  90 READY         7e974   e3b3c0       0     0
tPortmapd  _portmapd      ff1688 100 PEND          7bdfc   ff1330      16     0
MLOG_STDOUT_start_mlog_   e6c638 100 PEND          94950   e6c0a8       0     0
cserv      _cserv         e53db0 100 PEND          7bdfc   e537a8       0     0
responder  _responder     e130f0 100 PEND          94950   e11d88       0     0
rccd       _rccd          e2d1d0 150 PEND+T        7bdfc   e2ced8  3d0004    39
value = 0 = 0x0

Launch the restart script:
-> < restart
startup("/vx/force5ce/deimos/vme.deifcs/hosts/dsp",0)
Sending hardware reset to VMEINF board
Resetting VMEINF-2 by writing 0 to 6efff004
interrupt: Unknown level 15 Interrupt!
Sending STP command to TIMING board
Sending LOR command to TIMING board
RD bias voltages have all been set to minimum voltage
UTB application 0 test location= 10
UTB digital output= ff80
Analog switches in dewar electronics commanded open
Analog switches in dewar electronics indicate open
Sending hardware reset to TIMING board
msg size = 2 words.  reply size = 2 words
msg = 0X102 0X54544852
reply = 0X10002 0X444f4e
Sending STP command to TIMING board
Will verify vmeinf eprom against /vx/force5ce/deimos/vme.deifcs/hosts/dsp/vmeinf/vme.s
VMEINF board verification status= 0, should be 0
Will verify timing eprom against /vx/force5ce/deimos/vme.deifcs/hosts/dsp/timing/timing.s
TIMING board verification status= 0, should be 0
Will verify utility eprom against /vx/force5ce/deimos/vme.deifcs/hosts/dsp/utility/util.s
Expecting 1 verification error: at 800081
verify error: at address 800081  expected: 000004  got: 052d79
EOF
UTILITY board verification status= 1, should be 1
EEPROMs verified correctly. Proceeding with power-up
+5v readback raw ADC reading = 3413 volts= 4.991480 prior to enables
+15v readback raw ADC reading = 3486 voltage = 15.971211 prior to enable
-15v readback raw ADC reading = 616 voltage = -16.102915 prior to enable
+30v readback raw ADC reading = 2048 volts = 0.000000 prior to enable
UTB digital output= ff80
+/-15v power enabled
+5v readback raw ADC reading = 3416 volts= 5.002450 after 15v enable
+15v readback raw ADC reading = 3486 voltage = 15.971211 after 15v enable
-15v readback raw ADC reading = 617 voltage = -16.091669 after 15v enable
+30v readback raw ADC reading = 2048 volts = 0.000000 after 15v enable
UTB digital output= fe80
+30v power enabled
+5v readback raw ADC reading = 3416 volts= 5.002450 prior after enables
+15v readback raw ADC reading = 3487 voltage = 15.982318 after enables
-15v readback raw ADC reading = 617 voltage = -16.091669 after enables
+30v readback raw ADC reading = 3284 volts = 34.679161 after enables
Analog switches in dewar electronics commanded open
Analog switches in dewar electronics indicate open
Bias and clock voltages have been set, but not yet sent to CCD
Bias voltages for CCD 1
CCD 1 bias  0 ADC 3435 ( d6b) MUX  2.026 Volts 20.258  Vdd-1
CCD 1 bias  1 ADC 3435 ( d6b) MUX  2.026 Volts 20.258  Vdd-2
CCD 1 bias  2 ADC 2868 ( b34) MUX  1.196 Volts 11.959  RD-A
CCD 1 bias  3 ADC 2868 ( b34) MUX  1.196 Volts 11.959  RD-B
CCD 1 bias  4 ADC 1709 ( 6ad) MUX -0.498 Volts -0.996  OG-A
CCD 1 bias  5 ADC 2047 ( 7ff) MUX -0.003 Volts -0.006  Spare-2
CCD 1 bias  6 ADC 2047 ( 7ff) MUX -0.003 Volts -0.033  Guard ring
CCD 1 bias  7 ADC 2051 ( 803) MUX  0.003 Volts  0.003  Substrate
CCD 1 bias  8 ADC 3390 ( d3e) MUX  1.961 Volts  3.921  Spare-1
CCD 1 bias  9 ADC 1709 ( 6ad) MUX -0.498 Volts -0.996  OG-B
CCD 1 bias 10 ADC 2047 ( 7ff) MUX -0.003 Volts -0.006  Spare-3
CCD 1 bias 11 ADC 2047 ( 7ff) MUX -0.003 Volts -0.029  Bi-polar Spare
CCD 1 bias 12 ADC 2047 ( 7ff) MUX -0.003 Volts  0.000  Ground
CCD 1 bias 13 ADC 2047 ( 7ff) MUX -0.003 Volts  0.000  Ground
CCD 1 bias 14 ADC 2047 ( 7ff) MUX -0.003 Volts  0.000  Ground
CCD 1 bias 15 ADC 2047 ( 7ff) MUX -0.003 Volts  0.000  Ground
Bias voltages for CCD 2
CCD 2 bias  0 ADC 3436 ( d6c) MUX  2.027 Volts 20.273  Vdd-1
CCD 2 bias  1 ADC 3436 ( d6c) MUX  2.027 Volts 20.273  Vdd-2
CCD 2 bias  2 ADC 2868 ( b34) MUX  1.196 Volts 11.959  RD-A
CCD 2 bias  3 ADC 2868 ( b34) MUX  1.196 Volts 11.959  RD-B
CCD 2 bias  4 ADC 1709 ( 6ad) MUX -0.498 Volts -0.996  OG-A
CCD 2 bias  5 ADC 2047 ( 7ff) MUX -0.003 Volts -0.006  Spare-2
CCD 2 bias  6 ADC 2048 ( 800) MUX -0.002 Volts -0.018  Guard ring
CCD 2 bias  7 ADC 2051 ( 803) MUX  0.003 Volts  0.003  Substrate
CCD 2 bias  8 ADC 3388 ( d3c) MUX  1.958 Volts  3.915  Spare-1
CCD 2 bias  9 ADC 1709 ( 6ad) MUX -0.498 Volts -0.996  OG-B
CCD 2 bias 10 ADC 2047 ( 7ff) MUX -0.003 Volts -0.006  Spare-3
CCD 2 bias 11 ADC 2047 ( 7ff) MUX -0.003 Volts -0.029  Bi-polar Spare
CCD 2 bias 12 ADC 2047 ( 7ff) MUX -0.003 Volts  0.000  Ground
CCD 2 bias 13 ADC 2047 ( 7ff) MUX -0.003 Volts  0.000  Ground
CCD 2 bias 14 ADC 2047 ( 7ff) MUX -0.003 Volts  0.000  Ground
CCD 2 bias 15 ADC 2047 ( 7ff) MUX -0.003 Volts  0.000  Ground
Open bias voltages are all within tolerance
Low-rail clock voltages for clock gen 1
CLKGEN 1 clock  0 ADC 1504 ( 5e0) MUX -0.796 Volts -7.965
CLKGEN 1 clock  1 ADC 1504 ( 5e0) MUX -0.796 Volts -7.965
CLKGEN 1 clock  2 ADC 1503 ( 5df) MUX -0.798 Volts -7.980
CLKGEN 1 clock  3 ADC 1708 ( 6ac) MUX -0.498 Volts -4.978
CLKGEN 1 clock  4 ADC 1692 ( 69c) MUX -0.521 Volts -5.212
CLKGEN 1 clock  5 ADC 1692 ( 69c) MUX -0.521 Volts -5.212
CLKGEN 1 clock  6 ADC 1691 ( 69b) MUX -0.523 Volts -5.227
CLKGEN 1 clock  7 ADC 1692 ( 69c) MUX -0.521 Volts -5.212
CLKGEN 1 clock  8 ADC 1691 ( 69b) MUX -0.523 Volts -5.227
CLKGEN 1 clock  9 ADC 1707 ( 6ab) MUX -0.499 Volts -4.993
CLKGEN 1 clock 10 ADC 2047 ( 7ff) MUX -0.001 Volts -0.015
CLKGEN 1 clock 11 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 1 clock 12 ADC 1504 ( 5e0) MUX -0.796 Volts -7.965
CLKGEN 1 clock 13 ADC 1503 ( 5df) MUX -0.798 Volts -7.980
CLKGEN 1 clock 14 ADC 1503 ( 5df) MUX -0.798 Volts -7.980
CLKGEN 1 clock 15 ADC 1708 ( 6ac) MUX -0.498 Volts -4.978
CLKGEN 1 clock 16 ADC 1692 ( 69c) MUX -0.521 Volts -5.212
CLKGEN 1 clock 17 ADC 1692 ( 69c) MUX -0.521 Volts -5.212
CLKGEN 1 clock 18 ADC 1691 ( 69b) MUX -0.523 Volts -5.227
CLKGEN 1 clock 19 ADC 1691 ( 69b) MUX -0.523 Volts -5.227
CLKGEN 1 clock 20 ADC 1692 ( 69c) MUX -0.521 Volts -5.212
CLKGEN 1 clock 21 ADC 1707 ( 6ab) MUX -0.499 Volts -4.993
CLKGEN 1 clock 22 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 1 clock 23 ADC 2049 ( 801) MUX  0.001 Volts  0.015
High-rail clock voltages for clock gen 1
CLKGEN 1 clock  0 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 1 clock  1 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 1 clock  2 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 1 clock  3 ADC 2388 ( 954) MUX  0.498 Volts  4.978
CLKGEN 1 clock  4 ADC 2368 ( 940) MUX  0.469 Volts  4.685
CLKGEN 1 clock  5 ADC 2369 ( 941) MUX  0.470 Volts  4.700
CLKGEN 1 clock  6 ADC 2368 ( 940) MUX  0.469 Volts  4.685
CLKGEN 1 clock  7 ADC 2368 ( 940) MUX  0.469 Volts  4.685
CLKGEN 1 clock  8 ADC 2368 ( 940) MUX  0.469 Volts  4.685
CLKGEN 1 clock  9 ADC 2388 ( 954) MUX  0.498 Volts  4.978
CLKGEN 1 clock 10 ADC 2456 ( 998) MUX  0.597 Volts  5.974
CLKGEN 1 clock 11 ADC 2456 ( 998) MUX  0.597 Volts  5.974
CLKGEN 1 clock 12 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 1 clock 13 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 1 clock 14 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 1 clock 15 ADC 2389 ( 955) MUX  0.499 Volts  4.993
CLKGEN 1 clock 16 ADC 2368 ( 940) MUX  0.469 Volts  4.685
CLKGEN 1 clock 17 ADC 2369 ( 941) MUX  0.470 Volts  4.700
CLKGEN 1 clock 18 ADC 2368 ( 940) MUX  0.469 Volts  4.685
CLKGEN 1 clock 19 ADC 2369 ( 941) MUX  0.470 Volts  4.700
CLKGEN 1 clock 20 ADC 2368 ( 940) MUX  0.469 Volts  4.685
CLKGEN 1 clock 21 ADC 2388 ( 954) MUX  0.498 Volts  4.978
CLKGEN 1 clock 22 ADC 2456 ( 998) MUX  0.597 Volts  5.974
CLKGEN 1 clock 23 ADC 2456 ( 998) MUX  0.597 Volts  5.974
Low-rail clock voltages for clock gen 2
CLKGEN 2 clock  0 ADC 1504 ( 5e0) MUX -0.796 Volts -7.965
CLKGEN 2 clock  1 ADC 1504 ( 5e0) MUX -0.796 Volts -7.965
CLKGEN 2 clock  2 ADC 1503 ( 5df) MUX -0.798 Volts -7.980
CLKGEN 2 clock  3 ADC 1503 ( 5df) MUX -0.798 Volts -7.980
CLKGEN 2 clock  4 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock  5 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock  6 ADC 1504 ( 5e0) MUX -0.796 Volts -7.965
CLKGEN 2 clock  7 ADC 1504 ( 5e0) MUX -0.796 Volts -7.965
CLKGEN 2 clock  8 ADC 1504 ( 5e0) MUX -0.796 Volts -7.965
CLKGEN 2 clock  9 ADC 1503 ( 5df) MUX -0.798 Volts -7.980
CLKGEN 2 clock 10 ADC 2046 ( 7fe) MUX -0.003 Volts -0.029
CLKGEN 2 clock 11 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 12 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 13 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 14 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 15 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 16 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 17 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 18 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 19 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 20 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 21 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 22 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 23 ADC 2048 ( 800) MUX  0.000 Volts  0.000
High-rail clock voltages for clock gen 2
CLKGEN 2 clock  0 ADC 2183 ( 887) MUX  0.198 Volts  1.977
CLKGEN 2 clock  1 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 2 clock  2 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 2 clock  3 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 2 clock  4 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock  5 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock  6 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 2 clock  7 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 2 clock  8 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 2 clock  9 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 2 clock 10 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 11 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 12 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 13 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 14 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 15 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 16 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 17 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 18 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 19 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 20 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 21 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 22 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 23 ADC 2048 ( 800) MUX  0.000 Volts  0.000
Open clock voltages are all within tolerance
Switch states set to select clock low rails
RD bias voltages have all been set to minimum voltage
Analog switches commanded closed.
Analog switches in dewar electronics indicate closed
+5v readback raw ADC reading = 3417 volts= 5.006107 after closure
+15v readback raw ADC reading = 3486 voltage = 15.971211 after closure
-15v readback raw ADC reading = 617 voltage = -16.091669 after closure
+30v readback raw ADC reading = 3281 volts = 34.594990 after closure
RD has been commanded to nominal voltage
CCD is now powered up.
Bias voltages for CCD 1
CCD 1 bias  0 ADC 3419 ( d5b) MUX  2.002 Volts 20.024  Vdd-1
CCD 1 bias  1 ADC 3419 ( d5b) MUX  2.002 Volts 20.024  Vdd-2
CCD 1 bias  2 ADC 2868 ( b34) MUX  1.196 Volts 11.959  RD-A
CCD 1 bias  3 ADC 2868 ( b34) MUX  1.196 Volts 11.959  RD-B
CCD 1 bias  4 ADC 1709 ( 6ad) MUX -0.498 Volts -0.996  OG-A
CCD 1 bias  5 ADC 2048 ( 800) MUX -0.001 Volts -0.003  Spare-2
CCD 1 bias  6 ADC 2048 ( 800) MUX -0.002 Volts -0.018  Guard ring
CCD 1 bias  7 ADC 2050 ( 802) MUX  0.001 Volts  0.001  Substrate
CCD 1 bias  8 ADC 3390 ( d3e) MUX  1.961 Volts  3.921  Spare-1
CCD 1 bias  9 ADC 1709 ( 6ad) MUX -0.498 Volts -0.996  OG-B
CCD 1 bias 10 ADC 2047 ( 7ff) MUX -0.003 Volts -0.006  Spare-3
CCD 1 bias 11 ADC 2047 ( 7ff) MUX -0.003 Volts -0.029  Bi-polar Spare
CCD 1 bias 12 ADC 2047 ( 7ff) MUX -0.003 Volts  0.000  Ground
CCD 1 bias 13 ADC 2047 ( 7ff) MUX -0.003 Volts  0.000  Ground
CCD 1 bias 14 ADC 2047 ( 7ff) MUX -0.003 Volts  0.000  Ground
CCD 1 bias 15 ADC 2047 ( 7ff) MUX -0.003 Volts  0.000  Ground
Bias voltages for CCD 2
CCD 2 bias  0 ADC 3419 ( d5b) MUX  2.002 Volts 20.024  Vdd-1
CCD 2 bias  1 ADC 3419 ( d5b) MUX  2.002 Volts 20.024  Vdd-2
CCD 2 bias  2 ADC 2868 ( b34) MUX  1.196 Volts 11.959  RD-A
CCD 2 bias  3 ADC 2868 ( b34) MUX  1.196 Volts 11.959  RD-B
CCD 2 bias  4 ADC 1709 ( 6ad) MUX -0.498 Volts -0.996  OG-A
CCD 2 bias  5 ADC 2048 ( 800) MUX -0.001 Volts -0.003  Spare-2
CCD 2 bias  6 ADC 2048 ( 800) MUX -0.002 Volts -0.018  Guard ring
CCD 2 bias  7 ADC 2051 ( 803) MUX  0.003 Volts  0.003  Substrate
CCD 2 bias  8 ADC 3388 ( d3c) MUX  1.958 Volts  3.915  Spare-1
CCD 2 bias  9 ADC 1709 ( 6ad) MUX -0.498 Volts -0.996  OG-B
CCD 2 bias 10 ADC 2047 ( 7ff) MUX -0.003 Volts -0.006  Spare-3
CCD 2 bias 11 ADC 2047 ( 7ff) MUX -0.003 Volts -0.029  Bi-polar Spare
CCD 2 bias 12 ADC 2047 ( 7ff) MUX -0.003 Volts  0.000  Ground
CCD 2 bias 13 ADC 2048 ( 800) MUX -0.001 Volts  0.000  Ground
CCD 2 bias 14 ADC 2048 ( 800) MUX -0.001 Volts  0.000  Ground
CCD 2 bias 15 ADC 2048 ( 800) MUX -0.001 Volts  0.000  Ground
Closed bias voltages are all within tolerance
Low-rail clock voltages for clock gen 1
CLKGEN 1 clock  0 ADC 1505 ( 5e1) MUX -0.795 Volts -7.950
CLKGEN 1 clock  1 ADC 1504 ( 5e0) MUX -0.796 Volts -7.965
CLKGEN 1 clock  2 ADC 1504 ( 5e0) MUX -0.796 Volts -7.965
CLKGEN 1 clock  3 ADC 1708 ( 6ac) MUX -0.498 Volts -4.978
CLKGEN 1 clock  4 ADC 1692 ( 69c) MUX -0.521 Volts -5.212
CLKGEN 1 clock  5 ADC 1692 ( 69c) MUX -0.521 Volts -5.212
CLKGEN 1 clock  6 ADC 1692 ( 69c) MUX -0.521 Volts -5.212
CLKGEN 1 clock  7 ADC 1692 ( 69c) MUX -0.521 Volts -5.212
CLKGEN 1 clock  8 ADC 1691 ( 69b) MUX -0.523 Volts -5.227
CLKGEN 1 clock  9 ADC 1707 ( 6ab) MUX -0.499 Volts -4.993
CLKGEN 1 clock 10 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 1 clock 11 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 1 clock 12 ADC 1504 ( 5e0) MUX -0.796 Volts -7.965
CLKGEN 1 clock 13 ADC 1503 ( 5df) MUX -0.798 Volts -7.980
CLKGEN 1 clock 14 ADC 1503 ( 5df) MUX -0.798 Volts -7.980
CLKGEN 1 clock 15 ADC 1707 ( 6ab) MUX -0.499 Volts -4.993
CLKGEN 1 clock 16 ADC 1692 ( 69c) MUX -0.521 Volts -5.212
CLKGEN 1 clock 17 ADC 1692 ( 69c) MUX -0.521 Volts -5.212
CLKGEN 1 clock 18 ADC 1691 ( 69b) MUX -0.523 Volts -5.227
CLKGEN 1 clock 19 ADC 1692 ( 69c) MUX -0.521 Volts -5.212
CLKGEN 1 clock 20 ADC 1692 ( 69c) MUX -0.521 Volts -5.212
CLKGEN 1 clock 21 ADC 1708 ( 6ac) MUX -0.498 Volts -4.978
CLKGEN 1 clock 22 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 1 clock 23 ADC 2049 ( 801) MUX  0.001 Volts  0.015
High-rail clock voltages for clock gen 1
CLKGEN 1 clock  0 ADC 2185 ( 889) MUX  0.201 Volts  2.006
CLKGEN 1 clock  1 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 1 clock  2 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 1 clock  3 ADC 2388 ( 954) MUX  0.498 Volts  4.978
CLKGEN 1 clock  4 ADC 2369 ( 941) MUX  0.470 Volts  4.700
CLKGEN 1 clock  5 ADC 2368 ( 940) MUX  0.469 Volts  4.685
CLKGEN 1 clock  6 ADC 2368 ( 940) MUX  0.469 Volts  4.685
CLKGEN 1 clock  7 ADC 2369 ( 941) MUX  0.470 Volts  4.700
CLKGEN 1 clock  8 ADC 2369 ( 941) MUX  0.470 Volts  4.700
CLKGEN 1 clock  9 ADC 2389 ( 955) MUX  0.499 Volts  4.993
CLKGEN 1 clock 10 ADC 2456 ( 998) MUX  0.597 Volts  5.974
CLKGEN 1 clock 11 ADC 2456 ( 998) MUX  0.597 Volts  5.974
CLKGEN 1 clock 12 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 1 clock 13 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 1 clock 14 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 1 clock 15 ADC 2388 ( 954) MUX  0.498 Volts  4.978
CLKGEN 1 clock 16 ADC 2369 ( 941) MUX  0.470 Volts  4.700
CLKGEN 1 clock 17 ADC 2369 ( 941) MUX  0.470 Volts  4.700
CLKGEN 1 clock 18 ADC 2368 ( 940) MUX  0.469 Volts  4.685
CLKGEN 1 clock 19 ADC 2369 ( 941) MUX  0.470 Volts  4.700
CLKGEN 1 clock 20 ADC 2369 ( 941) MUX  0.470 Volts  4.700
CLKGEN 1 clock 21 ADC 2389 ( 955) MUX  0.499 Volts  4.993
CLKGEN 1 clock 22 ADC 2456 ( 998) MUX  0.597 Volts  5.974
CLKGEN 1 clock 23 ADC 2456 ( 998) MUX  0.597 Volts  5.974
Low-rail clock voltages for clock gen 2
CLKGEN 2 clock  0 ADC 1505 ( 5e1) MUX -0.795 Volts -7.950
CLKGEN 2 clock  1 ADC 1504 ( 5e0) MUX -0.796 Volts -7.965
CLKGEN 2 clock  2 ADC 1504 ( 5e0) MUX -0.796 Volts -7.965
CLKGEN 2 clock  3 ADC 1503 ( 5df) MUX -0.798 Volts -7.980
CLKGEN 2 clock  4 ADC 2046 ( 7fe) MUX -0.003 Volts -0.029
CLKGEN 2 clock  5 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock  6 ADC 1506 ( 5e2) MUX -0.794 Volts -7.936
CLKGEN 2 clock  7 ADC 1504 ( 5e0) MUX -0.796 Volts -7.965
CLKGEN 2 clock  8 ADC 1504 ( 5e0) MUX -0.796 Volts -7.965
CLKGEN 2 clock  9 ADC 1503 ( 5df) MUX -0.798 Volts -7.980
CLKGEN 2 clock 10 ADC 2047 ( 7ff) MUX -0.001 Volts -0.015
CLKGEN 2 clock 11 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 12 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 13 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 14 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 15 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 16 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 17 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 18 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 19 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 20 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 21 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 22 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 23 ADC 2048 ( 800) MUX  0.000 Volts  0.000
High-rail clock voltages for clock gen 2
CLKGEN 2 clock  0 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 2 clock  1 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 2 clock  2 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 2 clock  3 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 2 clock  4 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock  5 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock  6 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 2 clock  7 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 2 clock  8 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 2 clock  9 ADC 2184 ( 888) MUX  0.199 Volts  1.991
CLKGEN 2 clock 10 ADC 2049 ( 801) MUX  0.001 Volts  0.015
CLKGEN 2 clock 11 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 12 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 13 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 14 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 15 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 16 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 17 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 18 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 19 ADC 2049 ( 801) MUX  0.001 Volts  0.015
CLKGEN 2 clock 20 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 21 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 22 ADC 2048 ( 800) MUX  0.000 Volts  0.000
CLKGEN 2 clock 23 ADC 2048 ( 800) MUX  0.000 Volts  0.000
Closed clock voltages are all within tolerance
Now commanding shutter closed
+5v readback raw ADC reading = 3419 volts= 5.013420 prior to clocking
+15v readback raw ADC reading = 3486 voltage = 15.971211 prior to clocking
-15v readback raw ADC reading = 617 voltage = -16.091669 prior to clocking
+30v readback raw ADC reading = 3277 volts = 34.482758 prior to clocking
Sending IDL command to TIMING board
CCD clocks are now running in idling mode
value = 0 = 0x0